Noise Tolerant Techniques in Super and Sub-threshold Regions of TSPC logic
نویسندگان
چکیده
In this paper a technique is presented which improves the noise immunity of TSPC circuit. This technique is compared with other existing techniques. Analysis is carried out both for super and sub-threshold regions of operation. Investigations consider different performance criteria viz. n ooise immunity curve, power consumption, delay, average noise threshold energy (ANTE), PANTE and DANTE. The new technique gives better results in the form of improved noise immunity of the TSPC logic. It is found that power dissipation is decreased by over three orders in sub-threshold regime. Scaled technology offers better noise immunity in sub-threshold regime. Simulation results are presented for 180nm technology node.
منابع مشابه
Noise Tolerant Techniques in Super and Sub-threshold Regions of TSPC
In this paper a technique is presented which improves the noise immunity of TSPC circuit. This technique is compared with other existing techniques. Analysis is carried out both for super and sub-threshold regions of operation. Investigations consider different performance criteria viz. n ooise immunity curve, power consumption, delay, average noise threshold energy (ANTE),
متن کاملDynamic Logic Styles with Improved Noise-immunity
Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE by 3.4 and 2.8 over conventional dynamic True Single-Phase-Clock (TSPC) ...
متن کاملNoise Tolerant Circuits for Modified Feedthrough Logic
In this paper a circuit design technique to improve noise tolerant of a new CMOS domino logic family called feedthrough logic is presented. The feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (average noise threshold energy) metric...
متن کاملDesign of Cost Efficient Noise Tolerant Digital VLSI Circuits based on Probabilistic methods
Noise in digital logic circuits does not reduce with the scaling down of CMOS devices. The conventional CMOS design does not provide noise immunity when the circuits are operated in the sub threshold region. In order to enhance the performance of the circuit and to handle the errors caused due to noise that are random and dynamic in nature, a cost effective probabilistic based noise tolerant ci...
متن کاملA Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates
The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...
متن کامل